64Mb EPCS64 serial configuration device.Of interest to this project, the board contains.
ESP8266 WiFi SoC serving an HTTP API for control of the unit.My custom circuit board the provides a place to hook up the FPGA and LED tile to, and supplies power.Nios II core CPU for transferring graphics into the pixel buffer.Logic for pushing a memory pixel buffer to the tile and managing the timing of the R, G, and B LED components to create the illusion of colour mixing.PlatformIO to build the ESP8266 firmware.My circuit or something else to power the board and FPGA and connect them together.A Terasic DE0-Nano FPGA or something like it.New ESP8266 firmware can be done over the air, but the FPGA configuration and Nios II are loaded over a USB cable. Uses a Terasic DE0-Nano FPGA with a Nios II core soft CP running the Micrium μC/OS-II RTOS kernel, a custom circuitboard, and an ESP8266 serving an HTTP API for controlling it. This is an FPGA-driven WiFi connected 32x32 LED tile that I hang on my wall.
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